Critical Thinking Problems with solution on Unit 1 and 2

Q 1) What is wrong with the below vhdl snippet? How can you make it right?

process(a)
begin
 c = a xor b;
end process;

Ans:-

The problem is with the sensitivity list of the process. Inside the process, two signals 'a' and 'b' are read. For the code to correctly work in simulation, you have to add all the signals read inside a process, in its sensitivity list. So the correct version  would be,

process(a,b)
begin
 c = a xor b;
end process;



Q 2) When I try to synthesis the following process in Xilinx, I get an error. Why?

process(Clk1,Clk2)
begin
    if(rising_edge(Clk1)) then
        dout <= '1';
    elsif(rising_edge(Clk2)) then
        dout <= '0';
    end if;
end process;

Ans:-

When you try to synthesis, a synthesis error will be displayed saying, "Signal dout cannot be synthesized, bad synchronous description". 
This is because you are trying to change the signal dout with respect to two clocks. To implement an edge sensitive statement, a flip flop has to be used. And most of the current software tools don't support a dual edge sensitive flip flop. This is why you get an error.

Q3) Can you give an example in VHDL where a latch can be created. Also describe how you can change the code, so that the latch can be avoided.
Ans:-

The below process will create a 1 bit latch for dout signal.

process(din)
begin
    if(din = "00") then
        dout <= '1';
    elsif(din = "01") then
        dout <= '0';    
    end if;
end process;

A latch is inferred when the output of a combinational logic has undefined states, that is when it must hold its previous value. In the above example, you can see that the value of the output is not directly mentioned for input values "10" and "11". That is why the latch is created.

Its recommended that latches are to be avoided unless you want them intentionally in your design. They cause timing problems. To avoid latch, just make sure that you mention all the input to combinations to drive the output. See the modified process below:

process(din)
begin
    if(din = "00") then
        dout <= '1';
    elsif(din = "01") then
        dout <= '0';    
    else
        dout <= '0';
    end if;
end process; 

Q4) Write a VHDL snippet for swapping two one bit signals. First time assume they are signals and next time assume that they are variables.

Ans:-

Assuming the bits to swapped are signals:

signal A,B : std_logic;
process(Clk)
begin
    if(rising_edge(Clk)) then
        A <= B;
        B <= A;
    end if; 
end process;

Assuming the bits to swapped are variables:

process(Clk)
variable A,B,temp : std_logic;
begin
    if(rising_edge(Clk)) then
        temp := A;
        A := B;
        B := A;
    end if; 
end process;

So what is difference here? In VHDL, the signals are updated at the same time(concurrently) while the variables are updated one after the other(sequentially). This is why we needed a temp variable to swap the numbers, just like how we do in a C program.

Q5) What does the below code do?

entity q5 is 
   port(
      A : in std_logic_vector(7 downto 0);
      B : out std_logic_vector(11 downto 0)
        );
end q5;

architecture Behavioral of q5 is 
begin 

process(A)
begin
    B <= (A(7) & A(7) & A(7) & A(7)) & A;
end process;

Ans:-

The code has an 8 bit input and 12 bit output. The input and output signals are declared as std_logic_vector's. But in the code, they are assumed to store signed numbers in twos complement format. The sign of the number is determined by the MSB.
Output B is a sign extended version of input A. The concatenation operator, '&' is used for filling the 4 most significant bits of B with MSB of A.

Q6) Is it possible to implement a flip flop inside a VHDL function?
Ans:-

No. A flip flop is an edge sensitive element. But a VHDL function is used to implement a purely combinational circuit. We cannot check the positive or negative edge of a clock signal inside a function.

Q7) How do I initialize a VHDL signal to all zero's or all one's?
Ans:-

You can use others statement to do this:
signal A : std_logic_vector(7 downto 0) := (others => '0');     --to make all zeros
signal A : std_logic_vector(7 downto 0) := (others => '1');     --to make all ones

Q8) Anything wrong the the below code?
process(A)
begin
    if(A = '1') then
        C <= '1';
    else
        C <= '0';
    end if;
end process;

process(B)
begin
    if(B = '1') then
        C <= '0';
    else
        C <= '1';
    end if;
end process;

Ans:-

Yes. The code will return a synthesis error, "Multi-source in Unit <xxx> on signal <C>; this signal is connected to multiple drivers."

This error occurs when we try to drive a signal in more than processes. To remove this error, combine both the processes into a single one.

Q9) Write a VHDL code which take a signal din as input and dout as output. The signal dout is the same as din except that it is delayed by two clock cycles.

Ans:-

You can create delays in many ways in VHDL. This is just one way. 

signal A,B : std_logic;
process(Clk)
begin
    if(rising_edge(Clk)) then
        A <= din;
        B <= A;

        dout <= B;
    end if; 
end process;

Q10) Give an example for synchronous and asynchronous logic.

Ans:-

Synchronous logic is executed at the edge of a clock transition while asynchronous logic executes irrespective of clock transitions.