VLSI
Tuesday, August 20, 2019
Wednesday, July 24, 2019
VLSI Design and Technology Projects
Draw state diagram, write VHDL code, write test bench
code and implement using Spartan-III kit.
1. VCR Controller:
Implement a VCR controller as a Moore FSM.
The user controls the motion as follows:
Pressing
the Play button causes the tape to play.
Pressing the FF button causes the tape to advance:
Without playing, if stopped.
Scanning, if in play mode.
Pressing the Stop button causes the tape to stop.
Pressing the Rew button causes the tape to rewind:
Without playing, if stopped.
Scanning, if in play mode.
Pressing the FF button causes the tape to advance:
Without playing, if stopped.
Scanning, if in play mode.
Pressing the Stop button causes the tape to stop.
Pressing the Rew button causes the tape to rewind:
Without playing, if stopped.
Scanning, if in play mode.
Note: I
haven’t specified all transitions possible...
Outputs: Forward, Reverse,
Fast, HeadReading
2. Combinational Lock 1:
A 3-bit serial combination
lock is used to allow entry into a locked room.
The lock has RESET button, an
ENTER button, and a two-position switch to represent the key being entered. When the signal UNLOCK is asserted, an
electromechanical relay is released, allowing the door to open. The unlock process begins when the operator
presses RESET. He or she then sets the
input switch, followed by pressing the ENTER button. This is repeated for the second and third key
digits. An ERROR light should be illuminated
if, after entering the three binary digits, the operator has not matched the
key. The process can be started again by
hitting reset again.
3.
Air
Lock Controller
Implement an airlock controller as a Moore FSM.
The airlock has two doors – insideDoor and outsideDoor.
These are controlled by the signals insideDoorOpen and outsideDoorOpen.
There are two buttons – insideRequest and outsideRequest.
The airlock pressure is controlled by a single signal –
pressurize. The pressurize/depressurize process takes 10 seconds.
A ten second timer is available. It has input StartTimer
and output TimeUp.
The reset state is:
Both doors closed. Airlock pressurized.
When a request button is pressed, the following must
happen:
- The
chamber is either pressurized or depressurized depending on which button
was pressed.
- The
appropriate door is opened for ten seconds and then closed.
- The
chamber’s pressure is inverted.
- The
opposite door is opened for ten seconds and then closed.
______________________________________________________________________
4. Combinational
Lock 2:
Design another combo lock controller as a Mealy FSM...
The combination is A-A-B-A-B-A. If this is entered, output “open”.
From any state, three B’s in a row will reset the lock to
it’s beginning state.
Whenever an out-of-sequence A occurs, an output “bell” is
asserted to raise an alarm.
Once the lock is open,
pressing either A or B will reset it to the beginning state.
5 Washing Machine Controller:
Design a washing machine
controller as a Moore FSM...
Operation: When start is pressed, goes through wash,
spin, rinse, spin cycles. If “double rinse” is selected, an extra rinse and
spin cycle is added.
Details: Must fill the tub with water before washing or
rinsing – output the signal “filltub” to do this. A timer is provided that
gives the appropriate amount of time for a wash, rinse, or spin cycle.
Outputs:
Filltub – turns on water to tub.
Agitate – turns on agitator for wash and rinse
Spin – turns on spinner
StartTimer – starts the wash/rinse/spin timer – the timer’s start input is rising-edge triggered
Agitate – turns on agitator for wash and rinse
Spin – turns on spinner
StartTimer – starts the wash/rinse/spin timer – the timer’s start input is rising-edge triggered
Inputs:
Start – starts a wash
Tubfull – true when tub is full of water
Double – true if user wants a double rinse
TimeUp – true when time for wash/rinse/spin is done
Start – starts a wash
Tubfull – true when tub is full of water
Double – true if user wants a double rinse
TimeUp – true when time for wash/rinse/spin is done
6.
6. Tennis Scorer:
Design a Moore finite state
machine that keeps track of score in a tennis game. Tennis is scored as follows:
•
There
are two players, A and B.
•
Scoring
starts at zero, which is known in tennis lingo as love.
•
As
a player wins games, his/her score advances as follows:
Love à 15 à 30 à 40 à Game
•
The
first one to achieve “Game” wins.
•
The
score 40-40 is known as deuce.
If the score is deuce, then the first player to win two
points in a row wins the game.
Your finite state machine will have synchronous inputs A,
which is true whenever A wins a point, and B, which is true whenever B wins a
point, and a reset input.
The outputs should be “A
wins” and “B wins”, asserted at the appropriate times. Each state should be labeled with the current
score of player A and player B (i.e. 15-Love or 40-15).
7.
7. Traffic
Light Controller:
n A
busy highway is intersected by a little used farmroad
n Detectors
C sense the presence of cars waiting on the farmroad
q with
no car on farmroad, light remain green in highway direction
q if
vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing
the farmroad lights to become green
q these
stay green only as long as a farmroad car is detected but never longer than a
set interval
q when
these are met, farm lights transition from Green to Yellow to Red, allowing
highway to return to green
q even
if farmroad vehicles are waiting, highway gets at least a set interval as green
n Assume
you have an interval timer that generates:
q a
short time pulse (TS) and
q a
long time pulse (TL),
q in
response to a set (ST) signal.
q TS
is to be used for timing yellow lights and TL for green lights
Prof. Dr. Sunita P. Ugale
Critical Thinking Problems with solution on Unit 1 and 2
Q 1)
What is wrong with the below vhdl snippet? How can you make it right?
entity q5 is
port(
A : in std_logic_vector(7 downto 0);
B : out std_logic_vector(11 downto 0)
);
end q5;
architecture Behavioral of q5 is
begin
process(A)
begin
B <= (A(7) & A(7) & A(7) & A(7)) & A;
end process;
Ans:-
The code has an 8 bit input and 12 bit output. The input and output signals are declared as std_logic_vector's. But in the code, they are assumed to store signed numbers in twos complement format. The sign of the number is determined by the MSB.
Output B is a sign extended version of input A. The concatenation operator, '&' is used for filling the 4 most significant bits of B with MSB of A.
Q6) Is it possible to implement a flip flop inside a VHDL function?
Ans:-
No. A flip flop is an edge sensitive element. But a VHDL function is used to implement a purely combinational circuit. We cannot check the positive or negative edge of a clock signal inside a function.
Q7) How do I initialize a VHDL signal to all zero's or all one's?
Ans:-
You can use others statement to do this:
signal A : std_logic_vector(7 downto 0) := (others => '0'); --to make all zeros
signal A : std_logic_vector(7 downto 0) := (others => '1'); --to make all ones
Q8) Anything wrong the the below code?
process(A)
begin
if(A = '1') then
C <= '1';
else
C <= '0';
end if;
end process;
process(B)
begin
if(B = '1') then
C <= '0';
else
C <= '1';
end if;
end process;
Ans:-
Yes. The code will return a synthesis error, "Multi-source in Unit <xxx> on signal <C>; this signal is connected to multiple drivers."
This error occurs when we try to drive a signal in more than processes. To remove this error, combine both the processes into a single one.
Q9) Write a VHDL code which take a signal din as input and dout as output. The signal dout is the same as din except that it is delayed by two clock cycles.
process(a)
begin
c = a xor b;
end process;
Ans:-
The problem is with the sensitivity list of the process. Inside the process, two signals 'a' and 'b' are read. For the code to correctly work in simulation, you have to add all the signals read inside a process, in its sensitivity list. So the correct version would be,
process(a,b)
begin
c = a xor b;
end process;
Q 2) When I try to synthesis the following process in Xilinx, I get an error. Why?
process(Clk1,Clk2)
begin
if(rising_edge(Clk1)) then
dout <= '1';
elsif(rising_edge(Clk2)) then
dout <= '0';
end if;
end process;
Ans:-
When you try to synthesis, a synthesis error will be displayed saying, "Signal dout cannot be synthesized, bad synchronous description".
This is because you are trying to change the signal dout with respect to two clocks. To implement an edge sensitive statement, a flip flop has to be used. And most of the current software tools don't support a dual edge sensitive flip flop. This is why you get an error.
Q3) Can you give an example in VHDL where a latch can be created. Also describe how you can change the code, so that the latch can be avoided.
Ans:-
The below process will create a 1 bit latch for dout signal.
process(din)
begin
if(din = "00") then
dout <= '1';
elsif(din = "01") then
dout <= '0';
end if;
end process;
A latch is inferred when the output of a combinational logic has undefined states, that is when it must hold its previous value. In the above example, you can see that the value of the output is not directly mentioned for input values "10" and "11". That is why the latch is created.
Its recommended that latches are to be avoided unless you want them intentionally in your design. They cause timing problems. To avoid latch, just make sure that you mention all the input to combinations to drive the output. See the modified process below:
process(din)
begin
if(din = "00") then
dout <= '1';
elsif(din = "01") then
dout <= '0';
else
dout <= '0';
end if;
end process;
Q4) Write a VHDL snippet for swapping two one bit signals. First time assume they are signals and next time assume that they are variables.
begin
c = a xor b;
end process;
Ans:-
The problem is with the sensitivity list of the process. Inside the process, two signals 'a' and 'b' are read. For the code to correctly work in simulation, you have to add all the signals read inside a process, in its sensitivity list. So the correct version would be,
process(a,b)
begin
c = a xor b;
end process;
Q 2) When I try to synthesis the following process in Xilinx, I get an error. Why?
process(Clk1,Clk2)
begin
if(rising_edge(Clk1)) then
dout <= '1';
elsif(rising_edge(Clk2)) then
dout <= '0';
end if;
end process;
Ans:-
When you try to synthesis, a synthesis error will be displayed saying, "Signal dout cannot be synthesized, bad synchronous description".
This is because you are trying to change the signal dout with respect to two clocks. To implement an edge sensitive statement, a flip flop has to be used. And most of the current software tools don't support a dual edge sensitive flip flop. This is why you get an error.
Q3) Can you give an example in VHDL where a latch can be created. Also describe how you can change the code, so that the latch can be avoided.
Ans:-
The below process will create a 1 bit latch for dout signal.
process(din)
begin
if(din = "00") then
dout <= '1';
elsif(din = "01") then
dout <= '0';
end if;
end process;
A latch is inferred when the output of a combinational logic has undefined states, that is when it must hold its previous value. In the above example, you can see that the value of the output is not directly mentioned for input values "10" and "11". That is why the latch is created.
Its recommended that latches are to be avoided unless you want them intentionally in your design. They cause timing problems. To avoid latch, just make sure that you mention all the input to combinations to drive the output. See the modified process below:
process(din)
begin
if(din = "00") then
dout <= '1';
elsif(din = "01") then
dout <= '0';
else
dout <= '0';
end if;
end process;
Q4) Write a VHDL snippet for swapping two one bit signals. First time assume they are signals and next time assume that they are variables.
Ans:-
Assuming the bits to
swapped are signals:
signal A,B : std_logic;
process(Clk)
begin
if(rising_edge(Clk)) then
A <= B;
B <= A;
end if;
end process;
process(Clk)
begin
if(rising_edge(Clk)) then
A <= B;
B <= A;
end if;
end process;
Assuming the bits to
swapped are variables:
process(Clk)
variable A,B,temp : std_logic;
begin
if(rising_edge(Clk)) then
temp := A;
A := B;
B := A;
end if;
end process;
So what is difference here? In VHDL, the signals are updated at the same time(concurrently) while the variables are updated one after the other(sequentially). This is why we needed a temp variable to swap the numbers, just like how we do in a C program.
Q5) What does the below code do?
process(Clk)
variable A,B,temp : std_logic;
begin
if(rising_edge(Clk)) then
temp := A;
A := B;
B := A;
end if;
end process;
So what is difference here? In VHDL, the signals are updated at the same time(concurrently) while the variables are updated one after the other(sequentially). This is why we needed a temp variable to swap the numbers, just like how we do in a C program.
Q5) What does the below code do?
entity q5 is
port(
A : in std_logic_vector(7 downto 0);
B : out std_logic_vector(11 downto 0)
);
end q5;
architecture Behavioral of q5 is
begin
process(A)
begin
B <= (A(7) & A(7) & A(7) & A(7)) & A;
end process;
Ans:-
The code has an 8 bit input and 12 bit output. The input and output signals are declared as std_logic_vector's. But in the code, they are assumed to store signed numbers in twos complement format. The sign of the number is determined by the MSB.
Output B is a sign extended version of input A. The concatenation operator, '&' is used for filling the 4 most significant bits of B with MSB of A.
Q6) Is it possible to implement a flip flop inside a VHDL function?
Ans:-
No. A flip flop is an edge sensitive element. But a VHDL function is used to implement a purely combinational circuit. We cannot check the positive or negative edge of a clock signal inside a function.
Q7) How do I initialize a VHDL signal to all zero's or all one's?
Ans:-
You can use others statement to do this:
signal A : std_logic_vector(7 downto 0) := (others => '0'); --to make all zeros
signal A : std_logic_vector(7 downto 0) := (others => '1'); --to make all ones
Q8) Anything wrong the the below code?
process(A)
begin
if(A = '1') then
C <= '1';
else
C <= '0';
end if;
end process;
process(B)
begin
if(B = '1') then
C <= '0';
else
C <= '1';
end if;
end process;
Ans:-
Yes. The code will return a synthesis error, "Multi-source in Unit <xxx> on signal <C>; this signal is connected to multiple drivers."
This error occurs when we try to drive a signal in more than processes. To remove this error, combine both the processes into a single one.
Q9) Write a VHDL code which take a signal din as input and dout as output. The signal dout is the same as din except that it is delayed by two clock cycles.
Ans:-
You can create delays in
many ways in VHDL. This is just one way.
signal A,B : std_logic;
process(Clk)
begin
if(rising_edge(Clk)) then
A <= din;
B <= A;
process(Clk)
begin
if(rising_edge(Clk)) then
A <= din;
B <= A;
dout <= B;
end if;
end process;
Q10) Give an example for synchronous and asynchronous logic.
Ans:-
Synchronous logic is executed at the edge of a clock transition while asynchronous logic executes irrespective of clock transitions.
end if;
end process;
Q10) Give an example for synchronous and asynchronous logic.
Ans:-
Synchronous logic is executed at the edge of a clock transition while asynchronous logic executes irrespective of clock transitions.
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Q 1) What is wrong with the below vhdl snippet? How can you make it right? process ( a ) begin c = a xor b ; end process ; A...
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AICTE-DST-Texas Instruments IICDC 2019 (India Innovation Challenge Design Contest 2019)
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